Address Decoder Faults and their Tests for Two-Port Memories
نویسندگان
چکیده
A two-port memory contains two duplicated sets of address decoders which operate independently. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced, together with the test strategy.
منابع مشابه
Consequences of Port Restrictions on Testing Address Decoder Faults in Two-Port Memories
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